The present invention relates to a high-speed semiconductor memory device, and more particularly to a semiconductor memory device operating with an address to which a bus inversion scheme is applied.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells selected by addresses inputted together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to input and output data at higher speed. To this end, internal circuits of the semiconductor memory device must be able to operate at high speed and transfer signals or data therebetween at high speed.
The operating speed of the semiconductor memory device can be increased by performing internal operations at higher speed or increasing the signal and data input/output speed. As one example, a double data rate (DDR) memory device can increase the data output speed by outputting data in synchronization with a falling edge as well as a rising edge of a system clock. Since the DDR memory device inputs and outputs two data per clock cycle via one input/output terminal in one cycle, its data input/output speed is faster than that of the existing semiconductor memory device. Recently, a semiconductor memory device capable of inputting or outputting four data in one cycle of a system clock was proposed. Although the data input/output speed of the semiconductor memory device is gradually increasing, an input/output speed of an address or command signal is unsatisfactory.
In a typical semiconductor memory device, an address is inputted together with an external operation command signal in synchronization with a rising edge of a clock. That is, the semiconductor memory device receives external address and operation command signal in synchronization with a rising edge of an external clock and performs an internal operation. However, as the operating speed of the semiconductor memory device is increasing, an address can be inputted two times in one cycle of the system clock.
Graphics double data rate version 5 (GDDR5) memory devices for graphic works are designed to receive addresses at a rising edge and a falling edge of an external clock. That is, the GDDR5 memory devices can receive the addresses two times in one cycle of the external clock. Thus, compared with the typical semiconductor memory device, the number of address pins is reduced or the operating speed can be increased by connecting extra pins to a power voltage terminal or a ground terminal. Since an external operation command signal is still inputted in synchronization with a rising edge of an external clock, the address input speed is two times faster than a command input speed.
Since the addresses are inputted two times in one cycle of the external clock, the address transition increases two times and a voltage toggling often occurs at the address input port, causing a lot of current consumption. As one example, a swing width of an address signal can be defined in a range from VIH(Vref+0.12V) at a logic high level to VIL(Vref−0.12V) at a logic low level. Therefore, if the transitions occur two times more than the conventional art, the power consumption will also increase.
As the signal input speed increases in the same time, a bus inversion scheme is applied to the semiconductor memory device in preparation for the increasing transitions. According to the bus inversion scheme, a previously transmitted value and a current value to be transmitted are compared with each other. When transitions occur more than half of a total bit number to be transferred, a signal transmitter transmits an inverted value of the current value to be transmitted, and a signal receiver recognizes the current value by inverting the received signal. On the other hand, when transitions occur less than half of the total bit number, the signal transmitter transmits the current value and the signal receiver recognizes the received signal as it is. At this point, the signal transmitter and the signal receiver additionally transmit indication control signals indicating whether they transmit the current value or its inverted value.
A case where the bus inversion scheme is applied to 8-bit bus will be described in more detail. For example, assuming that “00011100” is a previously transmitted signal and “00001010” is a current value to be transmitted, a transition should occur at 3 bits. In this case, since three bits of the total eight bits have only to be changed, the signal transmitter transmits the current value to be transmitted. If a value to be newly transmitted after the transmission of “00001010” is “11100111”, transmission should occur at six bits. In this case, transitions occur more than half of the total eight bits, thus increasing the power consumption. Therefore, using the bus inversion scheme, the signal transmitter inverts the values “11100111” to be transmitted, and transmits “00011000”. The signal transmitter activates the indication control signal and indicates that the transmitted value is the inverted value. In this manner, compared with the previously transmitted value “00001010”, transitions occur at 2 bits of the eight bits. Consequently, the power consumption can be reduced, compared with the case where the transitions occur at six bits.
If such a bus inversion scheme is applied to multi-bit address signals inputted from the outside, an address input rate is increasing and the power consumption is reduced. However, when carrying out the bus inversion scheme, an operation speed may be lowered, or an operation margin for internal operation may be reduced, degrading the whole operation stability of the semiconductor memory device. In particular, if a delay occurs in the input of the address signal, an operation of reading data from or writing data to a cell corresponding to an address signal becomes slow, degrading the performance of the semiconductor memory device.